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Stingray
Account closed
Registered: Feb 2003
Posts: 117 |
FASTER 3D GRAPHICS
I've heard it said before that the way the VIC chip addresses memory (8x8 cells) makes it slower fo rendering graphics because of the extra calculations needed. So what way would you have had the Commodore engineers design an alternative addressing mode so that 3D graphics could be calculated quicker? I would realy appreciate your ideas on this. |
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JackAsser
Registered: Jun 2002
Posts: 1989 |
Quote: Quoting JackAsserYeps, a second set of registers for the odd rows would do the trick indeed.
So if I include the extra circuitry will you make your portal engine more awesome for it?
BTW Any chance of getting a bigger 3D area? that would be a cool Doom maze :)
Sure, why not. However, for rapid testing I suggest to make a patch to VICE to test out your ideas, before actually implementing them in the HW. That would probably help you in prototyping, and it would certainly help me not coding in blind. :)
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Frantic
Registered: Mar 2003
Posts: 1627 |
I vote for "BAD VIC". :)
It has a nice 80s vibe to it. :) |
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JackAsser
Registered: Jun 2002
Posts: 1989 |
Quote: I vote for "BAD VIC". :)
It has a nice 80s vibe to it. :)
Maybe "Notorious V.I.C"? |
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PopMilo
Registered: Mar 2004
Posts: 145 |
Quote: PopMilo,
It would be possible, would you really want to use the low res mode though?
Yes, at least in port of Yoomp from Atari :)
Eor filling doesn't help in that case but repeating lines without cpu time would save thousands of cycles each frame...
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Krill
Registered: Apr 2002
Posts: 2847 |
Quote: Yes, at least in port of Yoomp from Atari :)
Eor filling doesn't help in that case but repeating lines without cpu time would save thousands of cycles each frame...
I think what this implies is actually having display lists akin to what's implemented on Atari8. (See http://en.wikipedia.org/wiki/ANTIC)
You set a memory pointer in the VIC to fetch register offset, write cycle number (i.e., the x position defined as the offset to the previous write) and value (3 bytes or less if restrictions like writing to $d011/16/17/18 (2 bits) only are applied), and write data given by that display list to the referenced VIC registers at the specified x position. (Re repeating lines: One of the extra registers would then determine which of the 8 lines per char line you want to display.)
You could actually use the so far unused border cycles reading the colour data 4-bit bus for that, although that'd make generating these lists a little harder and halve the maximum throughput. Alternative list modes would define fixed register or offset definitions outside the list to be able to trade off between list size and access range/write density.
The benefits are obvious: Having more VIC register writes per scanline, specifically in the bad lines, would delight every coder fancying smart VIC raster trickery and open up a whole new range of oldskool effects and cpu-cycle-cheap display modes :) |
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Oswald
Registered: Apr 2002
Posts: 5020 |
yes, a display list would be bloody cool. |
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Krill
Registered: Apr 2002
Posts: 2847 |
Yes, and while we're at it, why not have an easy sideborderless mode where the expansion would flip the $d016 38/40 column bit at the right x positions twice each line automatically? Or the same with $d017 to stretch sprites? Or similar with $d011 for easy FLI/repeated badlines/linecrunching? Oh the possibilities! :) |
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Martin Piper
Registered: Nov 2007
Posts: 634 |
I have a suspicion that having a display list writing to VIC registers during bad lines might not be so easy. This is because the VIC is controlling the whole of the memory bus and bandwidth, i.e. both phis, for the period of the bad line fetches. This is why the CPU is paused during a bad line.
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Krill
Registered: Apr 2002
Posts: 2847 |
This is true, but there are still 23 cycles left for register writes during a badline, and with something like interleaved CPU and display list register writes, more is possible than with only the CPU writes in the cycles left. |
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PopMilo
Registered: Mar 2004
Posts: 145 |
"Display list" is maybe little to much but that is up to stingray to say :)
But those 20+ cycles could definitely be used in some way.
I thought about few bites somewhere in memory that would say to "VIC-III" :) how many lines to repeat.
Values would be 0,1,3 and would only manipulate data on address bus. One line down from bad line VIC would think its getting data from next 40bytes, while VIC-III would change those addresses back to previous 40 bytes... and so on...
Great idea with putting new hardware between VIC and rest of system !!! :)
I don't remember, is VIC in a socket or soldered ?
How hard will it be to insert this contraption ? :)
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