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Kisiel
Account closed
Registered: Jul 2003
Posts: 56 |
Short lines DMA access to VIC registers.
Hello,
I want to present DMADisplayList method to save CPU time. I think that is not great invention but in this method you can write to VIC registers in 'bad lines' too.
Following movie shows D021 change in each raster line. Grey vertical bar indicates physical write to register that I use to debug hardware routines(TDC). Display List takes 63 cycles in this example and it's in loop.
http://www.megaupload.com/?d=P8A8HNJ2 |
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PopMilo
Registered: Mar 2004
Posts: 145 |
If I understood it correctly, this is done with help of your TDC hardware ?
How do you manage to write into VIC registers while VIC is reading ram ? (I thought there would be a problem with double access to ram ?). |
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Kisiel
Account closed
Registered: Jul 2003
Posts: 56 |
Yes, you can access VIC register with additional hardware,only.
Due to access in bad lines, on movie you can see letter "l" it's value for register d021 (src is showed).DL can access vic register but value will be used by vic as char byte, 3 cycles later. I've thought that VIC reads data 12pix before it appears on screen, but it isn't true. it's 24pix.
FIFO pipe in VIC is much longer as we can see.
For coders information: I think it's a reason why FLI bug exists. |
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PopMilo
Registered: Mar 2004
Posts: 145 |
How are your results compared with info in vic article ?
Details of fli bug are explained in "VIC article".
http://ftp.giga.or.at/pub/c64/library/VIC-Article
What would happen if you would move "vertical bar" to 2-3 characters left of column 0 of screen - into border, and change border color instead of paper ?
Would "I" be visible on screen then ?
There is lots of stuff happening in those few chars in left part of border. If you can experiment with it - would be great!
Or something like that ? (Maybe I'm missing the point) :)
This is great stuff that you are making, keep on good work!
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Kisiel
Account closed
Registered: Jul 2003
Posts: 56 |
Quote: How are your results compared with info in vic article ?
Details of fli bug are explained in "VIC article".
http://ftp.giga.or.at/pub/c64/library/VIC-Article
What would happen if you would move "vertical bar" to 2-3 characters left of column 0 of screen - into border, and change border color instead of paper ?
Would "I" be visible on screen then ?
There is lots of stuff happening in those few chars in left part of border. If you can experiment with it - would be great!
Or something like that ? (Maybe I'm missing the point) :)
This is great stuff that you are making, keep on good work!
Vic article" The memory access and the display are separate function units
and the read graphics data is not immediately displayed on the screen
(there is a delay of 12 pixels)."
The delay is 24 pixels as you can see on the film.
If I move write cycles before the screen area (for my hardware first char on screen is cycle 15) nothing appears on screen between cycle 1 and 11 (DL can write 6 times to registers from end of H-blank). Cycle 12 => bug on first char
cycle 13 => bug on second char... So conclusion is: if you trying to put value to register of vic in area of 3 chars before screen, VIC will fetch this value for display data pipe, or my analyse is wrong due to facts.
I think in FLI technique writing to D011 or d018 "resets" pipe or CPU repeats reading from memory during 3 cycles before AEC signal goes LOW. For me second explanation is much true.
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PopMilo
Registered: Mar 2004
Posts: 145 |
Quote: Vic article" The memory access and the display are separate function units
and the read graphics data is not immediately displayed on the screen
(there is a delay of 12 pixels)."
The delay is 24 pixels as you can see on the film.
If I move write cycles before the screen area (for my hardware first char on screen is cycle 15) nothing appears on screen between cycle 1 and 11 (DL can write 6 times to registers from end of H-blank). Cycle 12 => bug on first char
cycle 13 => bug on second char... So conclusion is: if you trying to put value to register of vic in area of 3 chars before screen, VIC will fetch this value for display data pipe, or my analyse is wrong due to facts.
I think in FLI technique writing to D011 or d018 "resets" pipe or CPU repeats reading from memory during 3 cycles before AEC signal goes LOW. For me second explanation is much true.
Second explanation sounds more like it...
Cool experiments btw :)
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